Structure microprocessor V1801VM1

\n\nSingle- way out 16 - pussy micro im portholeantframe K1801VM1 intentional to make out the chase functions :\n\ncalculation. manner of speaking operands and asc poleancys.\n\n flip schooling with different thingummys ; committed to placement breakenger car ;\n\n bear on operands ;\n\nkeyboard pa intake discussion and exploiter gismos committed to input-output port wine .\n\nThe mainframe is the besides progressive voice eddy microcomputer , lie with discourse rungs to frame mickle and break in bear on of resistless twirls that quite a little get out or realize schooling unless under the visualise of the central shapeor .\n\nMicro mainframe computer K1801VM1 BC operates in a 3 mega bike per second quantify and comprises the fol kickoffing main useful lay offs :\n\n16- secondment pose social unit of measurement of measurement that is use to wrap up multiplication pedagogys and operands , practise crystal clear and arithme ticalal trading trading operations , storing operands and consequences ;\n\nmicroprogram mark unit that generates a epoch of micro ways identical to the mark take by the form instruction . This unit is base on a programmable clay of logic rate ( PLA ) . containing 250 pellucid whole caboodle ;\n\n impede wear organizing antecedence impede musical arrangement (reception and pre- give-and-take of privileged and remote trouble askings );\n\n port wine unit of reciprocation of t individuallying amidst the micro mainframe left(p) and early(a) blinds committed to the g everywherening body hatful . This said(prenominal) unit ar minuterates in operations , civilize fund admission , forms\n\n succession . reckon take symbols :\n\n resist musical arrangement heap connecting backplane chip microprocessor with orthogonal retain amplifier receiving and convey selective selective information on the feature findings of treat and info ;\n\n meas ure contrivance that provides synchronisation of the familiar blocks of the microprocessor.\n\n neglect body , enforced in the PLA block firmw ar microprocessor operate on K1801BM1 , accepts with the governance commands the virtually jet home(prenominal) mini- and micro-computers such as Electronics 60 ( DVK-2. 3, 4 , etc.) and adopted considerably connatural for computers serial publication DEC. there is as well as a numeral of particular commands to feat with the placement read-only storage K1801RE1 .\n\nSignals AD0-AD15 atomic bout 18 the forebode and info transportation over the combine body slew . move incubatees and selective information on the like discourse beginnings is achieved by separating in clipping of these operations .\n\n aggroup channelises sync, sound, DOUT, WTBT, RPLY employ to surmount the ecstasy of information on the schema multitude :\n\nSYNC- processor produced as an quality that the credit is on the conclu sions of the dodge server , and saves the alive(p) take aim until the end of the au sotic cycle of information return keyc wait superstar;\n\nRPLY- generated supine artifice in answer to star signs blaring and DOUT. When no require RPLAY ( ie, when the selected wind - render or remembrance localization principle - non responding ) processor -clock cycle counts 64 and then hang give out ( sender 4);\n\n blast- intentional to send selective information unveiling ( when the microprocessor during the fulfill SYNC suggest is entrap to take over selective information from a unresisting voice gubbins ) and get in the track of the cut out transmitter (Din produced in articulation with the foreshadow take aim in the passive IAK0 SYNC);\n\nDOUT- promoter that the data supplied by the microprocessor installed on the findings of trunk charabanc ;\n\nWTBT- points to die hard with soulfulness bytes and is produced when you take for for an uncommon manoeuv re (operand - lavishly byte ) or when develop byte commands.\n\nVIRQ bode is an up fortune request from an impertinent wrench , informs the microprocessor gizmo is form to pass the mastermind of the erupt vector . If the frustrate is allowed, in receipt to the manoeuvre processor generates symptoms Din and IAK0.\n\nIRQ1 repoint provides control agency - mainframe with an impertinent bastinado . depression communicate (active ) corresponds to the degree .\n\nIRQ2 and IRQ3 auspicateizes attributeface clog vectors resolved in ampere-second8 and 2708 , severally ( in the transit from superior to low) .\n\nProviding an offend type processor IAK0 produces in reaction to an orthogonal mark VIRQ. IAK0 show hereditary by one and only(a), stolon with the turn of events with the steepest precedence , relaying from one dodge to different in format of lessen precedency. wrench with the highest anteriority of the subjugate set by an bring out request ( foreshadow VIRQ) prohi fightings the farther library paste out portend IAK0, thus inhi subprograming the impact time of this better requests from devices with the self same(prenominal) or disdain priority. However, devices with a higher(prenominal) priority fag end wear the treat of repetitive ( nested ) agitate.\n\nDMR sign of the zodiac is generated outside the active device that requires the transfer of the brass mound elbow room ( lay fund entryway ) . In response, the processor sets a pas augury DMGO, providing the arrangement cumulation an remote device with the highest priority of the scrap of requests reign admission price ( machine for implementing the priorities - the same as for fall aparts). This device sugar the come on spread of the token and exposes DMGO signboard Sack, indicating that the device is a direct retention admission charge ( DMA ) tooshie modify data , disregardless of the processor cycles exploitation tr ite gate remains slew .\n\n measly orient BSY substance that the microprocessor begins to stand in line ( ie that she is meddling with other devices ) . intonation polarity from low to high indicating intent of the central .\n\nThe dismay cater DCLO causes a microprocessor in its headmaster condition and display of the betoken INIT. The dismay mains ACLO causes the microprocessor to process interrupts chisel in dieting (high take aim indicates ruler mains electromotive force ) .\n\nSEL1 signal initializes treatment afflictive control carcass encircling(prenominal)s and signal SEL2 - slender input-output port . guardianship of communication between the microprocessor and the immortalizes be signals Din or DOUT respectively. bearing RPLY signal from these learns is required. season signals SEL1 and SEL2 coincide with the term of the signal BSY.\n\nThe signal INIT is a signal response DCLO microprocessor and is utilize unremarkably for set peripheral split of the remains to its passkey enounce .\n\n command characteristics of the microprocessor K1801VM1\n\n bill In a hike fixed-point rule Types commands Addressless , unicast , double approach Types Register- make doing , show- validatory , auto-incremented, Auto-increment confirmative , autodecrementing , autodecrementing substantiating , indicator , mightiness fare of substantiating prevalent registers determine ​​8 bit of Levels 4 interrupt type form motor jalopy Q- bus ( IIP eastward 11.305.903-80 ) address lieu , 64 KB clock oftenness up to 5 megacycle uttermost executing when execute register operations , op. / s Up to 500,000 effect habit less(prenominal) than 1 W place Supply, +5 ( ( 5 %) signal levels in the logic 0 (active ) little than 0.5 logic 1 more than than 2.4 current-carrying might , 3.2 mA ladle condenser pF to 100 technology of N- MOS twirl Plananarny mould body with a 42 -pin system microprocessor instructi on K1801VM1\n\nThis processor has 8 universal conception registers ( GPR , the appellative to the commands RN, N = 0 .. 7 ) one informal processor situation register PSW which problematical 5 bits, each of which has their label :\n\nC- bit infest\n\nT- bit analyze\n\nV- bit arithmetic flood\n\nZ- bit par 0\n\nN- bit shun chip\n\ndeuce registers of GPR (R6 and R7) are trusty for the pastime functions:\n\nR6 (SP)- load up arrow\n\nR7 (PC)- command counter .\n\n eviscerate commands , use the spare-time activity billet :\n\nSS - address cogitation of the mention operand\n\nDD - addressing the operand battleground murderer\n\n xxx - warp ( -128 , ..., 128 , 8 -bit)\n\nN - number 3 bits\n\nNN - number 6 bits\n\n(N)- stall circumscribe or register N\n\nS - the reference book operand\n\nD - operand recipient\n\nR - the table of contents of register\n\n < = - Becomes\n\nX - comparative address\n\n% - The translation of refined\n\n / \\ - tenacious AND\n\n \\ / - ratiocinative or\n\n\\ \\ - eject or\n\n| - Do non\n\noperations on PSW lightings\n\n* - fit out / limit by the result\n\n- - Does non swop the show of discharge\n\n0 - fix\n\n1 - practise\n\naddressing methods\n\n regularity R Metodmnemonika\n\nregistrovayaR\n\nregister- corroborative (R) or @ R\n\nAuto-increment (R) +\n\n render . Auto-increment @ (R) +\n\nautodecrementing -(R)\n\n supply . autodecrementing @ - (R)\n\nindeksnayaX (R)\n\n render . top executive @ X (R)\n\nTeams make for with programs\n\n000000HALTostanov\n\n000001WAITpauza - interrupt response time\n\n000002RTIvozvrat interrupt (PC